|Thursday, June 2|
Preparing for Supercomputing’s Sixth Wave
Author: Jeffrey S. Vetter
Date: Thursday 9:45am - 10:45am
Abstract:After five decades of sustained progress, Moore's law appears to be reaching its limits. In order to sustain the dramatic improvements to which we have become accustomed, computing will need to transform to Kurzweil's sixth wave of computing. The supercomputing community will likely need to re-think most of its fundamental technologies and tools, spanning innovative materials and devices, circuits, system architectures, programming systems, system software, and applications. We already see evidence of this transition in the move to new architectures that employ heterogeneous processing, non-volatile memory, multimode memory hierarchies, and optical interconnection networks. In this talk, I will recap progress in these areas over the past three decades, discuss current solutions, and contemplate various future technologies that our community will need for continued progress in supercomputing. [Slide]
Bio:Jeffrey Vetter, Ph.D., is a Distinguished R&D Staff Member at Oak Ridge National Laboratory (ORNL). At ORNL, Vetter is the founding group leader of the Future Technologies Group in the Computer Science and Mathematics Division. Vetter also holds joint appointments at the Computational Science and Engineering School of the Georgia Institute of Technology, and at the Electrical Engineering and Computer Science Department of the University of Tennessee-Knoxville. The coherent thread through his research is developing rich architectures and software systems that solve important, real-world high performance computing problems. Recently, he has been investigating the effectiveness of next-generation architectures, such as graphics processors, non-volatile memory systems, heterogeneous multicore processors, and field-programmable gate arrays (FPGAs), for important science applications. His papers have won awards at the International Parallel and Distributed Processing Symposium and EuroPar; he was awarded the ACM Gordon Bell Prize in 2010. His recent books “Contemporary High Performance Computing (Vols. 1 and 2)” survey the international landscape of HPC. Vetter is a Senior Member of the IEEE, and a Distinguished Scientist Member of the ACM. See his website for more information: http://ft.ornl.gov/~vetter/.
|Friday, June 3|
With Extreme Scale Computing the Rules Have Changed
Author: Jack Dongarra
Date: Friday 9:30am - 10:30am
Abstract:In this talk we will look at the current state of high performance computing and look at the next stage of extreme computing. With extreme computing there will be fundamental changes in the character of floating point arithmetic and data movement. In this talk we will look at how extreme scale computing has caused algorithm and software developers to changed their way of thinking on how to implement and program certain applications. [Slide]
Bio:Jack Dongarra holds an appointment at the University of Tennessee, Oak Ridge National Laboratory, and the University of Manchester. He specializes in numerical algorithms in linear algebra, parallel computing, use of advanced-computer architectures, programming methodology, and tools for parallel computers. He was awarded the IEEE Sid Fernbach Award in 2004; in 2008 he was the recipient of the first IEEE Medal of Excellence in Scalable Computing; in 2010 he was the first recipient of the SIAM Special Interest Group on Supercomputing’s award for Career Achievement; in 2011 he was the recipient of the IEEE IPDPS Charles Babbage Award; and in 2013 he received the ACM/IEEE Ken Kennedy Award. He is a Fellow of the AAAS, ACM.
|Saturday, June 4|
Implications of Heterogeneous Memories in Next Generation Server Systems
Author: Ada Gavrilovska
Date: Saturday 9:30am - 10:30am
Abstract:Next generation datacenter and exascale machines will iclude significantly larger amounts of memory, greater heterogeneity in the performance, persistence or sharing properties of the memory components they encompass, and increase in the relative cost and complexity of the data paths in the resulting memory topology. This poses several challenges to the systems software stacks managing these memory-centric platform designs. First, technology advances in novel memory technologies shift the data access bottlenecks into the software stack. Second, current systems software lacks capabilities to bridge the multi-dimensional non-uniformity in the memory subsystem to the dynamic nature of the work- loads it must support. In addition, current memory management solutions have limited ability to explicitly reason about the costs and tradeoffs associated with data movement operations, leading to limited efficiency of their interconnect use. To address these problems, next generation systems software stacks require new data structures, abstractions and mechanisms in order to enable new levels of efficiency in the data placement, movement, and transformation decisions that govern the underlying memory use. In this talk, I will present our approach to rearchitecting systems software and services in response to both node-level and system-wide memory heterogeneity and scale, particularly concerning the presence of non-volatile memories, and will demonstrate the resulting performance and efficiency gains using several scientific and data-intensive workloads. [Slide]
Bio:Dr. Ada Gavrilovska is a Senior Research Scientist at the College of Computing and the Center for Experimental Re- search in Computer Systems (CERCS) at Georgia Tech. Her research is centered on innovation of the systems software stack, driven by emerging hardware technologies, and focused on supporting data- and communication-intensive applications. Recent projects include systems software innovation in light of large-scale parallelism in multicores, platform- wide compute and memory heterogeneity, novel interconnect capabilities and increases in device-level computational re- source density. Gavrilovska’s research is supported by the National Science Foundation, the US Department of Energy, and industry grants, including from Cisco, HP, IBM, Intel, Intercontinental Exchange, LexisNexis, VMware, and others. She has published over eighty peer-reviewed papers, and edited a book "High Performance Communications: A Vertical Approach" (CRC Press, 2009). In addition to research, she also teaches courses on operating systems and high performance communications. She has a BS degree in Electrical Engineering from University Sts. Cyril and Methodius in Macedonia (’98), and a MS (’99) and PhD ('04) degrees in Computer Science from Georgia Tech.